1. Field of the Invention
The present invention relates to a laminated ceramic electronic component and a method for manufacturing the laminated ceramic electronic component, and more particularly, to a laminated ceramic electronic component including an external terminal electrode formed directly by plating so as to be electrically connected at least partially to a plurality of internal electrodes, and a method for manufacturing the laminated ceramic electronic component.
2. Description of the Related Art
Laminated ceramic electronic components typically include, for example, as in the case of a laminated ceramic capacitor, a component main body having a stacked structure, which includes a plurality of stacked ceramic layers, and a plurality of layered internal electrodes formed along the interfaces between the ceramic layers. The plurality of internal electrodes have respective ends exposed, for example, at each of first and second end surfaces of the component main body, and an external electrode is formed so as to electrically connect the respective ends of the internal electrodes to each other.
For the formation of the external electrodes, typically, a conductive paste containing a metal component and a glass component is applied onto the end surfaces of the component main body, and then subjected to firing, thereby forming paste electrode layers first. The paste electrode layers serve to electrically connect the internal electrodes to each other. Next, a first plating layer containing, for example, nickel as its main constituent is formed on the paste electrode layers, and a second plating layer containing, for example, tin or gold as its main constituent is further formed thereon. The second plating layer is intended to ensure solderability, whereas the first plating layer serves to prevent solder erosion in a solder joint.
As described above, the external electrodes are each typically composed of a three-layer structure of the paste electrode layer, the first plating layer, and the second plating layer.
However, the paste electrode layers have a large thickness of several tens μm to several hundreds μm. Therefore, in order to limit the dimensions of the laminated ceramic electronic component to within certain specifications, there is undesirably a need to reduce the effective volume for ensuring characteristics such as electrostatic capacitance, because there is a need to ensure the volume for the paste electrode layers. On the other hand, the plating layers each have a thickness on the order of several μm. Thus, if the external electrodes can be composed of only plating films, the effective volume can be ensured more for ensuring the electrostatic capacitance.
For example, Japanese Patent Application Laid-Open No. 63-169014 discloses a method for forming an external electrode terminal of a chip capacitor, characterized in that a conductive metal layer is deposited by electroless plating on the entire sidewall surfaces of a chip capacitor element, which are opposed to each other at each end, so as to short-circuit internal electrode layers exposed at the sidewall surfaces, when an external electrode terminal is formed on the chip capacitor element obtained by sintering after alternately stacking ceramic dielectric layers and the internal electrode layers.
In the method described in Japanese Patent Application Laid-Open No. 63-169014, the exposed ends of the internal electrode layers serve as nucleuses for plating deposition in the formation of the plating films to serve as external electrode terminals. Therefore, when the interval is increased between the exposed ends of the internal electrode layers, which are adjacent to each other, the plating film may fail to cover the intervals adequately. In fact, Japanese Patent Application Laid-Open No. 63-169014 discloses the fact that it has been determined that uniform and even favorable external electrode terminals can be formed in the case of ceramic dielectric layers of 30 μm or less in thickness and internal electrode layers of 1 μm or more.
It is to be noted that electroless plating is applied in the method described in Japanese Patent Application Laid-Open No. 63-169014. On the other hand, electrolytic plating is known to have a smaller potential for plating growth as compared with electroless plating. Accordingly, when electrolytic plating is applied for the formation of the plating films, the interval is required to be smaller between the exposed ends of the internal electrode layers, which are adjacent to each other.